Processor Configurable Sample Rate Converter for RISC-V and 5G Communication
Otto Simola, Andrei Spelman, Aleksi Korsman, Marko Kosunen, Jussi Ryynänen · 2024
In digitally-intensive transceiver systems, sample rate conversion is an elementary operation in transmitter and receiver signal data paths. In this work, we present a processor configurable sampling rate converter accelerator for RISC-V communications processor. The implementation aims for high energy efficiency through computational optimization of rate conversion functions, and high area efficiency with filter re-use through processor controlled configuration. The latter feature is especially important in systems that do not transmit and receive simultaneously. The converter is designed with Chisel hardware description language, and accessible through AXI4-Lite. The configuration makes possible a seamless integration to a RISC-V core as a hardware accelerator. The accelerator has been verified, in stand-alone mode and with the RISC-V processor for 5G compliance, using a Python-based RTL simulation framework. The configurability of the conversion direction lowers the occupied area compared to a two path design by 33.0%. With 16-bit accuracy, the converter introduces only 0.04% deviation in error vector magnitude and -81.75 dB adjacent channel leakage ratio with 5G signals.