Research on Low-Power FPGA Accelerator for Radar Detection
Shuaijie Liu, Kun Li, Jinyang Luo, Xiaolong Li · 2024
With the rapid development of deep learning technology, object detection models have shown great potential in various applications. However, the high computational requirements of this type of model have become a bottleneck for its widespread adoption on resource-constrained, energy-efficiency-first devices. The flexibility of FPGA allows for the deployment of the YOLO model on various hardware platforms, including embedded systems and edge devices. In summary, deploying the YOLO model on FPGA can achieve real-time, low-power object detection, providing efficient visual perception capabilities for various application scenarios. This paper is based on the YOLOv2 radar detection algorithm and utilizes hardware FPGA acceleration for target detection. The system has been verified to provide target detection with low power consumption. Compared to the CPU (i7-6700k), While maintaining as much accuracy as possible in detection, it saves about 23 times in terms of power consumption.