A New Semi-Analytical Model for Erase Transients of 3-D Gate-All-Around (GAA) NAND Flash Memories
Jinil Yoo, Haechan Choi, Hyungcheol Shin · IEEE Transactions on Electron Devices · 2024
In this article, we introduce a new semi-analytical model to calculate the erase (ERS) transients of 3-D gate-all-around (GAA) NAND flash memories. A previously proposed program (PGM) model is revised by adopting the amphoteric trap model (ATM). Injection/escape/back tunneling components are added and the influences of each are investigated. The proposed model makes a better fit with experimental data than the previous model and also successfully implements the back tunneling component.