CoChrono: A Unified Hardware/Software Performance Analysis Tool for SoC-FPGA Codesign
Fabien Portas, Guy Bois, Yvon Savaria · 2024
High-level embedded system design tools are making the design of complex SoC-FPGA systems more accessible than ever before. However, this comes at the cost of more opacity as implementations result from heavy transformations made by high-level synthesis tools, while there is a lack of complete suitable performance analysis tools for the resulting implementations. This paper proposes a unified application programmer interface and methodology that enables the extraction of time points to instrument performance metrics for hardware/software co-simulation and monitoring the SoC-FPGA execution. The proposed tool, called CoChrono, leverages high-level synthesis and code gener-ation to access metrics similarly in software and hardware C++ code. The tool's features and low overhead are demonstrated with a practical application of architecture exploration and simulation model validation. Compared to instruments manually inserted using existing tools, CoChrono significantly reduces the effort required to validate complex timing constraints in hardware/soft-ware systems.