Sophon: A Time-Repeatable and Low-Latency Architecture for Embedded Real-Time Systems Based on RISC-V
Zhe Huang, X Chen, Feng Gao, Ruige Li, Xiguang Wu, Fan Zhang · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2024
Embedded real-time systems impose rigorous timing constraints, where the failure to complete critical tasks within prescribed deadlines can lead to system crashes and catastrophic errors. Control latency, encompassing I/O and interrupt latency, significantly impacts system performance. Previous studies have primarily concentrated on architectural design to meet timing requirements or optimize for performance enhancement. Although the Ti programmable real-time unit (PRU) addresses both timing requirements and control latency, it remains a proprietary commercial chip. This article introduces a deterministic response architecture called Sophon, founded on the open and freely available reduced instruction set computer five (RISC-V). The essential part of this architecture is a tiny and flexible Sophon core that has fixed instruction latency. We propose an enhanced instruction set architecture (ISA) extension interface (EEI) capable of transmitting up to 32 operands in a single instruction, facilitating the development of domain-specific applications. In addition, we have devised two custom instructions to minimize control latency. The Sophon core requires a minimum of 28.6k gate equivalents. Experimental results demonstrate that the Sophon architecture eliminates execution time deviations while preserving low control latency. The highest achievable general purpose I/O (GPIO) flipping frequency is half of the core frequency, and the fastest interrupt latency is three clock cycles.