Digital Low Drop-out Regulator Based on Event-driven Operating Modes
Ashkan Pourmoslemi, Freddy Anstotz, Vincent Frick · 2024
This paper introduces a 1.8 V - 30 mA integrated Digital Low Drop-out Regulator (D-LDO) featuring dual clock speed, and event-driven operation presenting fine-tuning and stand-by modes. These features enhance the agility of the D-LDO over a wide range of load currents and ensure its high regulation responsiveness to load or supply line variations. They also minimize power consumption by deactivating internal components during stable conditions. The proposed D-LDO is designed and simulated in 180 nm CMOS technology, offering 81$\boldsymbol{\mu} \mathbf{A}$quiescent current and a minimal 1 pF load capacitor. It handles load current changes of 20 mA in less than 212 ns with a maximum output voltage droop of 385 mV. Its simple and compact architecture makes it suitable for miniature applications.