Hardware Design of Single-Precision Floating-Point Number Squaring Circuit Based on Modified Non-Restoring Algorithm
Da Huang, Huimin Liu, Qiang Dou, Zhuo Ma · 2024
The role of floating-point square root operations in scientific computing is important in numerous application areas. Its efficiency and accuracy directly impact system performance and result accuracy. However, the traditional floating-point square root algorithm has certain limitations in terms of speed and accuracy. This paper presents the hardware circuit structure of the improved Non-Restoring algorithm, implemented using a timing circuit. A Xilinx XC7A15T-2CPG236I FPGA was used for the simulation and performance evaluation of the hardware circuit implementation of the proposed algorithm. The results demonstrated that the hardware circuit required 149 storage units (LUTs), consumed 0.0028 W, and operated at a maximum frequency of 279 MHz. The hardware circuit proposed in this paper has 93.5% fewer LUTs, 97.6% lower power consumption, and 135.06 MHz higher frequency than the traditional hardware circuit. This reduction in power consumption is achieved without any loss of computational accuracy, as the frequency is increased. This new solution for floating-point square root arithmetic offers a significant improvement in both speed and hardware resource consumption.