CIPUF: Towards On-chip Learnable Anomaly Detection with Compute-In-PUF Architecture
Jianbo Liu, Boyang Cheng, Zephan M. Enciso, Steven Davis, Ningyuan Cao · 2024
With the rising threats of side-channel-attacks (SCA) and complexities of both on-chip and ambient environment, it is demanding to incorporate on-chip learnability into SCA anomaly detection. This will enable offline-trained models to adapt to the new power profiles of emerging SCA schemes, workloads, and varying environments. Existing SCA detection techniques often fall short in in-situ learning or pose excessive on-chip integration challenges due to resource and data demands. This paper presents a novel neuromorphic "compute-in-PUF" (CIPUF) architecture designed for SCA detection with on-chip learning capability and optimized area/energy/data overheads. We harness the PUF-based key generator as a hyperdimensional encoder, fostering few-shot learning capabilities. It showcases a state-of-the-art accuracy of 96% with offline training. While deployed on-chip, our architecture can adeptly re-calibrate its model at the introduction of unseen power profiles, and regain model accuracy by 45% with as few as 254 power trace samples during 0.45ms time frame. Meanwhile, compared with baseline design using separate PUF and learning modules, it achieves a area savings of 4.15X and energy savings of 12.8X. Nevertheless, it introduces a unique scalability advantages for both hardware key repository and learning accuracy for future technology.