ReOVE: Restricted Out-of-Order Execution for Superscalar Processors with Vector Extension
Masayuki Kimura, Ryota Shioya · 2024
Vector instructions have recently been introduced in general-purpose CPUs. These general-purpose CPUs typically employ out-of-order superscalar processors to execute scalar instructions at high speed. However, the naive implementation of vector instructions in an out-of-order CPU can require considerable circuit area due to the complex register and memory access inherent to vector instructions. While reordering between vector and scalar instructions is crucial for performance in out-of-order CPUs, we found that reordering among vector instructions does not significantly contribute to performance improvement. Based on this observation, we propose ReOVE, a novel architecture designed to implement vector instructions in out-of-order CPUs while maintaining low hardware costs by introducing partial restrictions on vector instruction reordering. We evaluated ReOVE on a cycle-accurate simulator with the RISC-V vector extension. The evaluation results show that ReOVE reduces the energy consumption and circuit area by 21.9% and 21.1%, respectively, with a performance degradation of 2.7% compared to existing out-of-order CPUs.