Sustainable Low-Power ALU and Multiplexer based AI Accelerator Design and Optimization Using Cadence
S. Padmapriya, S Sarveshware, Durai Murugan S, K Shree Harini, Raga Vendran R M · 2024
In today's fast-paced world, where time is of the essence and AI-generated content is becoming increasingly prevalent, the demand for efficient hardware accelerators is paramount. Accelerators are crucial for enhancing AI algorithms, requiring components like Arithmetic Logic Units, SRAM registers, memory elements, and multiplexers. Balancing performance with low power consumption is essential, driving researchers to focus on optimizing power, area, and frequency. To address these challenges, we propose leveraging Pass Transistor Logic to enhance power efficiency and reduce the Power-Delay Product and area in AI accelerators. By modifying components such as the ALU and Multiplexer blocks, we achieve significant reductions in power consumption and time delay. Our findings indicate substantial power savings (e.g., from 4.89mW to 2.5mW for the ALU block) and reduced delays (e.g., from 6 sec to 0.799 sec for the ALU block), showcasing the effectiveness of Pass Transistor Logic in improving both power efficiency and performance. This work contributes to the development of low-power, high-efficiency AI accelerators, aligning with the demands of our modernized society.