Ph.D. Project: A Compiler-Driven Approach to HW/SW Co-Design of Deep-Learning Accelerators
Tendayi Kamucheka, David Andrews · 2024
This work introduces SPAR, a compiler framework based on MLIR, tailored for deep learning inference applications. Alongside SPAR, we present SPAR HL, an extensible Instruction Set Architecture (ISA) designed to seamlessly interface custom FPGA-based accelerators with the SPAR compiler. Historically, custom accelerators on FPGA have posed a challenge as a compiler target. Prior compiler initiatives have addressed this issue by generating application-specific hardware during compilation, necessitating expertise across both application and hardware domains. In response, we offer an alternative approach by proposing an ISA as a unified compiler target and hardware interface for custom accelerators. Furthermore, we introduce a compiler capable of translating high-level machine learning models encoded in ONNX into code compatible with our proposed ISA, thus enabling efficient deployment on FPGA-based custom accelerators.