Address-Dependent Divided-Bit-Line NAND Flash Memory for Reduction in Latency and Energy
Yuta Sugisawa, Tôru Tanzawa · 2024
In this paper, we propose an address-dependent divided-bit-line (BL) NAND Flash memory for reduction in read latency. Energy in bit-line path can be also reduced with this design. A single switching MOSFET is added per BL. When a memory cell located closer to the sense amplifier is selected for read, the switch gets turned off. The sense amplifier sees shorter BL with smaller parasitic capacitance and resistance, resulting in lower latency and energy in BL path. When a memory cell located farther from the sense amplifier is selected for read, the switch gets turned on. The sense amplifier sees the original bit-line when the on-resistance of the switch is sufficiently low in comparison with the BL resistance. The averaged BL access time and energy can be minimized analytically when the switch is placed at xSW of 0.58 and 0.50, respectively, where xSW indicates the switch location (xSW = 0 at the closest to the sense amplifier and xSW = 1 at the farthest from the sense amplifier), assuming that the memory cells are accessed in random. With the proposed design, the average read latency and energy can be reduced to 62 % and 75 %, respectively. The effectiveness of the proposed design was validated with SPICE. This paper also investigates 1) the case where hot memory cells are placed in the closer side whereas cold cells are in the farther side and 2) the case where more switches are built in every BL. In this paper, NAND Flash memory is considered to quantifying the effectiveness of the proposed design on read latency and energy.