Hardware obfuscation-algorithmic transformation-based obfuscation for secure floorplan-driven high-level synthesis
Anirban Sengupta, Rahul Chaurasia · 2024
The chapter describes an integrated methodology that leverages algorithmic transformation-based obfuscation with crypto-watermarking for generating HLS-driven secure floorplan for loop-based IP designs (Sengupta and Kachave, 2017; Sengupta and Rathor, 2020; Sengupta et al., 2017). The significance is that most of the modern electronics systems are integrated with complex loop-based applications to perform important functions such as filtering, convolution, image processing, etc. Loop-based applications can deliver efficient performance if designed using dedicated hardware intellectual property (IP) cores using high-level synthesis (HLS). However, globalization in the design supply chain introduces security vulnerabilities during IP design that need robust countermeasures. More explicitly, the chapter presents a discussion on the following: (a) methodology for generating HLS-driven secure floorplan for loop unrolled hardware IPs; (b) integration of algorithmic transformation-based obfuscation with crypto-watermarking during HLS to provide sturdy detective countermeasure against IP piracy and false IP ownership claim, while simultaneously reducing latency; (c) security-aware physical design-based HLS that is capable to convert a loop-based high-level code (representing a computation-intensive application) into its respective early secure floorplan that considers watermark embedding information of the datapath modules.The rest of the chapter has been organized as follows: Section 9.1 provides the introduction of the chapter; Section 9.2 discusses prior similar methodologies; Section 9.3 provides details on methodology for algorithmic transformation-based obfuscation for secure floorplan-driven HLS; Section 9.4 provides a detailed analysis and discussion; and Section 9.5 concludes the chapter by summarizing the chapter's findings and implications.