A Three Dimensional DRAM (3D DRAM) Technology for the Next Decades
K.S. Choi, S.H. Kim, Jin-Woo Seo, H.S. Kang, S.W. Chu, Sang-Wook Bae, J.H. Kwon, G.S. Kim, Young‐Jun Park, J.H. Kwak, Dong-Il Song, Solmoi Park, Y. Kim, Kiyoub Jang, Jung Sang Cho, Ho‐Sung Lee, B.H. Lee, J.W. Park, J.H. Lee, Hyuk‐Chul Kwon · 2024
Three dimensional structured DRAM technology has drawn huge attention recently for its potential to fulfill high speed operation and low power consumption. In this paper, 3D DRAM with vertical bit line (BL) architecture is introduced as a promising solution to overcome scaling limitation for future DRAM technology. Full chip integration with 5-layered cell stacked on peri -core wafer is successfully demonstrated for the first time, offering superior on -current performance and gate controllability. A novel process integration scheme using Si/SiGe sacrificial multilayers and hybrid wafer bonding technique is presented with excellent full chip operation of 3D DRAM.