Demonstration of Logic-Block Performance-Power Gain by 1st Generation Back Side Power Delivery Network for SoC and HPC Applications Beyond 2nm Node
Hidenobu Fukutome, J. Kim, Joonghan Shin, J. Kim, Y Lee, Youngsoo Park, D Oh, S Chae, B. Eom, YS Nam, M Lee, Sanghyun Ha, E.G. Chung, J. Kim, M Jo, SH Lee, Sang Soo Kim, KH Cho, KW Lee, DW Kim · 2024
We have experimentally demonstrated effects of BSPDN on performance-power of standard cell featuring Gate-all-around (GAA) FETs scaled down for SoC technology beyond 2nm node for the first time. 1stgeneration (Gen) BSPDN provides high immunity of cell-level leakage with ultra-scaled cell height and we achieve 6% speed gain by optimizing metal routing. As a result, 1stGen BSPDN could make it possible to achieve 7.5% performance or 5% power gain compared to FSPDN with logic and SRAM test chip verification.