Co-Optimization for Robust Power Delivery Design in 3D-Heterogeneous Integration of Compute In-Memory Accelerators
Ankit Kaul, Madison Manley, James Read, Yandong Luo, Xiaochen Peng, Shimeng Yu, Muhannad S. Bakir · 2024
In this work, we quantify the impact of power supply noise (PSN) in 3D-HI architectures on the errors in ADC and RRAM array outputs and optimize the 3D PDN and ADC designs to maximize inference accuracy in compute-in-memory (CIM) hardware. We propose a device-HI -application-level evaluation methodology to evaluate the impact of PDN design parameters on CIM inference accuracy. For our assumed 3D CIM hardware, an areal distribution of through-silicon vias (TSVs) and u-bumps, and a fine-tuned PSN-aware successive approximation register-ADC (SAR-ADC) achieves a 90% inference accuracy compared to 47% with a baseline 3D design at iso-power and iso-area. These insights can be useful for multi -die design convergence for edge intelligent CIM chips.