Material, Process and System Level Analysis for Parasitic Reduction of Next Generation Logic Technology in Conjunction with Backside Power Delivery
Ashish Pal, Sefa Dag, Pratik B. Vyas, Gregory Costrini, Vinod Reddy, Veeraraghavan S. Basker, Allen Yeong, Benjamin P Colombeau, Bala Haran, Subi Kengeri, El Mehdi Bazizi · 2024
The first generation of backside power delivery network (BS-PDN Gen-1), implemented with a backside power via (BPV) has been shown to introduce additional parasitic capacitances, thus degrading the standard cell performance by 2.5% compared to FS-PDN, and limits the performance benefit at processor-level. In view of this, we propose an advanced metal gate-cut (MG-cut) process with low-K dielectric gate-cut fill for capacitance reduction. Our MSCO™ platform shows that BS-PDN circuit performance can be fully recovered with these 2 modifications. In addition, these modifications in combination with BSPDN, also improve SRAM read and write delay by 8% and 17%, thus bringing significant performance benefit for next generation GAA logic nodes.