ETCIM: An Error-Tolerant Digital-CIM Processor with Redundancy-Free Repair and Run-Time MAC and Cell Error Correction
Yiqi Wang, Zhen He, Chenggang Zhao, Zihan Wu, Mingyu Gao, Huiming Han, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin · 2024
This work presents an Error-Tolerant digital Computing-in-Memory (CIM) processor ETCIM. It has three key features to solve the hard error correction overhead, soft error correction incompatibility and latency problem of traditional methods on digital CIM: 1) A Fault-Adaptive CIM Initializer (FACI) and input feeder reduce the hard error repair overhead by up to 8.47x power and 18.16x area savings. 2) A Block-wise ECC (BW-ECC) CIM suits digital CIM's structure and corrects soft multiply-accumulation (MAC) errors; 3) A Progressive Cell Error Corrector (PCEC) hides soft cell error correction latency during computation, reducing the total latency by up to 96.8%.