Low Power CMOS based 4-2 Compressor Architecture Using XOR-XNOR and Multiplexers
Nampally Sai Rukmangad Rohit, Manoj Kumar · 2024
For mathematical circuits such as multipliers, this paper introduces a new design for a 4-2 compressor that is both fast and energy efficient. The proposed design utilizes a combination of XOR-XNOR gates and 2×1 Mux’s, to achieve improved power and delay metrics compared to existing 4-2 compressor implementations. By leveraging the availability of both valid and complementary output signals in XOR/XNOR circuits, the new architecture reduces the number of logic stages required, thereby decreasing propagation delay. Multiplexers are employed in the critical path to enhance speed performance further. The 4-2 compressor was designed and simulated using 90nm CMOS process technology in Cadence Virtuoso. The simulation results show the proposed 4-2 compressor achieves up to 25% lower power consumption and 12.6% lower propagation delay than previous works, making it suitable for low-power and high-performance VLSI applications.