A 1.8% FAR, 2 ms Decision Latency, 1.73 nJ/Decision Keywords-Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-IF-Domain Computing and Scalable 5T-SRAM
Fei Tan, Wei-Han Yu, Jinhai Lin, Ka-Fai Un, Rui Paulo Martins, Pui‐In Mak · IEEE Journal of Solid-State Circuits · 2024
This article reports a keyword-spotting (KWS) chip with a significantly reduced false alarm rate (FAR) for voice-control edge devices. The key techniques are threefold: 1) transfer-computing speaker verification (SV)-assisted KWS that compresses the required parameters and enhances the KWS+SV computation efficiency while maintaining the KWS accuracy and reducing the overall FAR; 2) hybrid-IF-domain computing that handles both the analog and digital input features (IFs), alleviating the tradeoff between the computation power and system accuracy of the first layer; and 3) scalable 5T-SRAM array that sustains the leakage and read power when it is upscaled. Benchmarking with the state-of-the-art, our SV-assisted KWS prototyped in 28-nm CMOS achieves the best-in-class energy efficiency of 1.73 nJ/decision, a decision latency of 2 ms, and a FAR of 1.8%. The achieved 12-class top-1 KWS accuracy is 91.8% for the Google speech command dataset (GSCD) and the core area is 0.121 mm2, including an 11-KB full SV-assisted KWS model. The described chip also shows the lowest-reported 12-class KWS power consumption of$1.73~{\mu }$W.