ScanCamouflage: Obfuscating Scan Chains with Camouflaged Sequential and Logic Gates
Tarik Ibrahimpašić, Grace Li Zhang, Michaela Brunner, Georg Sigl, Bing Li, Ulf Schlichtmann · 2024
Scan chain is a commonly used technique in testing integrated circuits as it provides observability and controllability of the internal states of circuits. However, its presence can make circuits vulnerable to attacks and potentially result in confidential internal data leakage. In this paper, we propose a novel technique for obfuscating scan chains using camouflaged flip-flops, which are designed with the same layout as the original flip-flops but have the actual functionality of a buffer. Furthermore, we employ camouflaged logic gates interconnected in special configurations to increase the difficulty of SAT attack. Experimental results demonstrate that circuits with only a small number of flip-flops can already be protected by the proposed technique while incurring only a minimal area overhead.