HT-TMR: An Efficient Netlist-Level TMR Tool for FPGA SEU Mitigation
Yaowei Zhang, Lei Chen, Shuo Wang, Jing Zhou, Chunsheng Tian, Yu Li, Yuanhang Bu, Yuxin Yu · 2024
This paper describes an efficient software tool HT-TMR tool, one of BMTI HongTu series software, developed to automatically apply TMR mitigation on FPGA design to protect against SEUs. The tool provides three preset TMR modes and a custom TMR mode for designers. Once the TMR mode is selected, the tool parses the input EDIF file, determines necessary points to insert the voters, and generates the newly constructed circuit in EDIF format which has the same functionality of the original. Compared with Mentor's Precision Hi-Rel tool, our tool has a lower resource utilization, better timing performance, and higher compatibility.