FlattenRTL: An Open Source Tool for Flattening Verilog Module at RTL Level
Xiangchen Meng, Ziyue Zheng, Yangdi Lyu · 2024
While hierarchy in the Register-Transfer Level (RTL) makes hardware designs more readable, reusable, and scalable, a flattened design by removing the hierarchy is useful for synthesis, verification, and optimization. For example, a flattened Verilog module can help the verification tools better analyze the dependencies of signals in exact instances. Therefore, a tool to flatten the Verilog modules at the RTL level is helpful in the electronic design automation (EDA) domain. Flattening the Verilog modules is a challenge with the ever-increasing complexity of hardware designs. According to our experiments, the existing tool to flatten Verilog modules in RTL is a proprietary tool from EDAUtils, which fails to pass the equivalence checking of the flattened module with the original modules in many benchmarks. In this paper, we proposed an innovative open-source tool called FlattenRTL to convert hierarchical RTL Verilog designs into a flattened, single-module form. FlattenRTL removes the hierarchy while preserving its functionality by employing code analysis and manipulation methods. Experimental results illustrate that the flattened modules pass equivalence checking in all benchmarks. In addition, FlattenRTL is more efficient than the existing proprietary Verilog flattening tool.