CAMLB-SpMV: An Efficient Cache-Aware Memory Load-Balancing SpMV on CPU
Jihu Guo, Rui Xia, Jie Liu, Xiaoxiong Zhu, Xiang Zhang · 2024
Sparse Matrix-Vector Multiplication (SpMV) plays a crucial role in scientific computing, but severe load imbalance among threads restricts its performance. Previous load-balancing methods have primarily ignored the CPU’s cache line-based memory access characteristics and the impact of data locality during workload evaluation and partitioning, leading to limited effect in load balancing.