Securing Test Infrastructure Against Test Based Side Channel Attacks
Kalakota Kiran Reddy, S Nagarjun Gowda, Gautham G Mulay, Hrithik L Jain, S S Rekha, K Sudeendra Kumar · 2024
This paper focuses on the growing problem of counterfeiting in the integrated circuits (IC’s) industry, specifically addressing the vulnerability to test based side channel attacks (TB SCA). The proposed security architecture utilizes a layered approach to protect IC’s from these risks. Key elements include integrating a Truly Random Number Generator (TRNG) and implementing key validation mechanisms to ensure authenticity. One time programmable (OTP) registers, encryption and integration of key into chains further enhance protection against access. Examining both functionality and structure of the architecture makes defense more powerful. When key validation fails, if fake responses are generated, it shows that system resistance to reverse engineering is strong. The approach not only protects intellectual property but also boosts general security of electronic systems that use these chips. In the face of security risks posed by counterfeiting this methodology represents a critical advancement in protecting semiconductor supply chains and ensuring the reliability of electronic systems worldwide thereby safeguarding both businesses and consumers against the pervasive threat of counterfeit IC’s.