High-Performance Error and Erasure Decoding With Low Complexities Using SPC-RS Concatenated Codes
Zhihao Zhou, Wei Zhang, Xinyi Guo, Jianhan Zhao, Yanyan Liu · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2024
In this brief, a novel single parity check-assisted error and erasure decoding (SPC-EED) algorithm over the compound channel is proposed for Reed-Solomon (RS) codes. EED is applied to the scheme of SPC-RS concatenation code. The proposed algorithm can correct most random errors with the assistance of SPC codes. Through using channel soft information, the symbols with burst errors can be identified accurately and efficiently for erasures in EED. Simulation results show that the SPC-EED algorithm can achieve coding gains of up to 0.1, 0.4, and 2.1 dB compared with burst-error correcting (BC)-SPC-ordered statistic decoding (OSD), BC-OSD, and BCHDD-low-complexity chase (LCC) for RS(255, 239) codes, respectively, at symbol error rate (SER) = 10−3. The proposed algorithm has lower computational complexities while maintaining better decoding performance. The hardware design of the SPC-threshold check module is provided. The implementation results in ASIC show that compared with the BCHDD-LCC decoder, the SPC-EED decoder improves area efficiency by 249.37% with higher energy efficiency.