Robust and Efficient RTL to C Compiler Optimized for High-Level Synthesis
Md Imtiaz Rashid, Benjamin Carrión Schäfer · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2024
Designing hardware at the register transfer level (RTL) using low-level hardware description languages (HDLs) like Verilog or VHDL gives designers large degrees of controllability to create hardware architectures that will meet the given cost, power budget and performance requirements. The main problem with this approach is that the manually optimized architecture is fixed, which implies that future redesigns to, e.g., target other hardware platforms like field-programmable gate arrays (FPGAs) or newer technologies nodes might require the redesign and reverification of the RTL description. This is error prone and time consuming. To address this, in this work, we propose an RTL to C compiler that generates C code optimized for high-level synthesis (HLS) such that the redesign and reoptimization of new hardware design can be automated. HLS has multiple significant advantages over traditional RT-level design flows like being able to design and verify the behavioral description once and then retarget it for different hardware platforms and constraints by simply using a new technology library and synthesis constraints. Moreover, HLS allows to generate multiple functional equivalent design variants with unique tradeoffs like area, performance, and power from the same behavioral description by setting synthesis options in the form or pragmas (comments) to mainly control how to synthesize arrays (RAM or registers) and loops (unroll, partially unroll, no unroll, or pipeline). In order to leverage these advantages, in this work, we introduce an RTL to C compiler framework that we call MIRROR: maximizing the reusability of RTL through RTL to C Compiler and its new improved version MIRROR++ that is able to compile back to C different types of RTL descriptions, including pipelined circuits, finite state machines, and circuits that share functional units generating arrays and loops so that these can in turn be resynthesized (HLS) with different synthesis directives. Experimental results show the effectiveness and robustness of our approach.