Fast Software Implementation of the SM4 Algorithm
Xin Li, Ming Xie, Chengwei Huang · 2024
SM4 serves as the national standard for symmetric block ciphers. Evaluating algorithm implementation performance relies heavily on the efficiency of encryption and decryption calculations. However, research concerning software implementation strategies for SM4 remains limited. This paper introduces a rapid software optimization approach for the SM4 algorithm, leveraging bit-slice techniques in conjunction with the AVX2 instruction set, which supports Single Instruction, Multiple Data (SIMD) operations. Through the utilization of 256-bit YMM registers, the proposed method achieves parallel encryption and decryption of 256 blocks of data for the SM4 algorithm. Initially, a novel selection function is devised based on existing ones, accompanied by enhancements to the search algorithm. Consequently, the logical expression of the S-box is simplified based on the new selection function and improved search algorithm. This simplification reduces the number of logic gates required for implementation from 3000 (in simplest AND-OR terms) to 497. On an Intel Core i7-10700 processor, the implementation speed attains 2630 Mbps, marking a 44% improvement compared to the best publicly available result of 1795 Mbps. The software optimization method, predicated on bit-slice techniques, circumvents the necessity for memory or high-speed cache table lookups, thereby fortifying resilience against cache-timing side-channel attacks and augmenting security. Furthermore, the proposed optimization method is scalable, applicable not only to X86 platforms employing the AVX2 extension instruction set but also to resource-constrained, high-security ARM and other embedded platforms utilizing RISC instruction sets. Additionally, the novel selection function and search algorithm are generic and can be adapted for the simplification of other general logic functions.