Hardware Acceleration Method Using RISC-V Core with No ISA Extensions
Mateusz Wygrzvwalski, Paweł Skrzypiec, Robert Szczygieł · 2024
We propose a method for hardware acceleration of different algorithms using a specially designed RISC-V core. Acceleration is handled by only CSR registers without adding any new instruction to the Instruction Set Architecture (ISA). The core microarchitecture was extended and it operates in several modes, which allow to speed up the code being executed. The core modification is a general purpose and can be applied to other cores. To be able to use the processor operating modes, the assembly code must be appropriately modified, as shown in the example of calculating the Number Theoretic-Transform (NTT). Thanks to such hardware/software approach we were able to reduce the number of cycles of the Kyber NTT algorithm by 30% compared to the optimized assembly program.