Deploying Artificial Intelligence in Design Verification to Accelerate IP/SoC Sign-off with Zero Escape
Surajit Bhattacherjee, Daksh Shah, Dipankar Pal · 2024
Design verification is a bottleneck in development of Intellectual Property (IP) subsystems and System-on-Chip (SoC). State-of-art verification processes practiced in VLSI-industries involve methodologies that are time-consuming, effort-hungry and expensive. They also have high possibilities of bug-escape for complex memory-intensive, computation-intensive, mathematical and logical design modules if the verification sign-off at the IP-SoC boundary is not tightly closed. The methodology proposed here recommends an alternate sign-off approach through Machine Learning (ML) applications on a complex design, namely, Temperature Sensor (TS) in Dual-In-line Memory Module (DIMM) of a Dynamic Random Access Memory (DRAM). Factual evidences derived from Random Forest classifier and regressor not only confirm behavioural accuracy of the Design Under Test (DUT) but also portray decision trees to visualize RTL implementation of the architectural specification. The experiment testifies a smooth integration of ML-adaptor for analyses of a formal verification data-set to claim faster debug-ability with high accuracy while predicting the output for sample stimuli to DUT.