Implementation of a Symmetric Double Arbiter Physical Unclonable Function and Evaluation the Impact of Temperature Influences using PYNQ-Z1 Board
Sinan Yavuz, Edwin Naroska, Kai Daniel · 2024
Deployment of delay-based Physical Unclonable Functions (PUF) on FPGAs for Internet-of-Things (IoT) network security is becoming increasingly important in research due to their lightweight structure and good statistical properties. PUFs can generate high reliable and device-unique keys that can be used in security applications such as authentication protocols or for IP protection to avoid cloning attacks. This can be achieved by exploiting the delay-time of the individual components of a PUF, which vary due to the fluctuation in the manufacturing process. However, a important challenge in the implementation of delay-based PUFs in order to achieve high reliability and uniqueness is a well-balanced and symmetric design layout. Unwanted offset delays can occur due to the unsymmetric wire routing, which may in turn have negative impacts on the quality metrics. In addition, physical fluctuations can also affect the behavioral of the PUF. This paper presents the implementation and evaluation of a lightweight 32-bit DAPUF (Double Arbiter-PUF) using PYNQZ1 board. For performance analysis, the design is implemented on three different PYNQ-Z1 boards and quality metrics such as reliability, uniqueness, randomness and bias are analyzed considering different ambient temperatures in a range of 0-50°C. In addition, an extended version of the proposed DAPUF (XORDAPUF) is simulated and also investigated. Our results show that the DAPUF is more sensitive to temperature fluctuations than XOR-DAPUF. In addition, our results clearly show that uniqueness, randomness as well as bias are improved compared to the results of the implemented DAPUF, which is close to the ideal value.