Design of Low-Power Low-Complexity High-Delay FlipFlop
D. Srinivas, Siva Sankara Reddy N, Rajendra Naik B · International Journal of Electrical and Electronics Engineering · 2024
The operation of deep sub-micron digital systems is dependent on power dissipation. Power is of the utmost importance in miniature systems. This work examines the use of traditional flip-flops. This work presents a unique master-slave flip-flop that combines fast speed with low power consumption. Master and slave latches make the flip-flop structure the most successful. In this paper, the flip-flop design uses 17 transistors in total to build master and slave circuits. The level of complexity, in particular, decreases with decreasing PMOS transistor count. This design produces a fast and compact flip-flop. The circuit in question employs a single clock. The proposed research has been modelled on the 45nm technology node. The present research includes PVT analysis to validate the reliability of the flip-flop. The proposed FF has a low power usage of at least 9.22%, less leakage power of at least 17.48%, and a clock-to-output delay of at least 68.37% when compared with the existing FFs.