A Hardware-Efficient Vector Limiter Algorithm and Its Programmable Logic Realization
Zhao Song, Yiyan Wang, Tianyi Xiong · 2024
Vector limiter is a computationally complex component of vector control, but its hardware-friendly algorithm is rarely discussed. This paper presents an efficient solution with pure shift-and-add operations, namely the dual vector rotation algorithm (DVRA). Its programmable logic realization is also provided. The DVRA is then simulated in a motor driving system, and physical validation is made on a Xilinx FPGA. Furthermore, performance comparison is conducted between the DVRA and four control groups (conventional algorithms). All control groups are built by Xilinx IPs under diversified configurations, thus human bias can be minimized. Post-implementation results evince that the DVRA exhibits significantly less resource expenditure and better timing, with power consumption and accuracy comparable to the control groups.