Implementing RISC-V processor with three-stage pipeline on FPGA
Qiao Zuo, Yujie Li, Liang Wei, Fan Jianning, Ku Hongxu, Xiaodong Zhang, Chong Shen · 2024
With the advent of the Internet of Things era, the demand for low-power, low-cost, scalable, open, and flexible chips is increasing day by day. This paper aims to design a RISC-V processor with a three-level pipeline structure, and verify its performance and functionality through verification on FPGA. The design process includes steps such as RTL design and simulation testing, RTL synthesis, constraints, Place and Route, burning, running program development and downloading, and running the built program on the RISC-V processor burned on FPGA. The kernel and peripheral design adopts a three-level pipeline design, and the functions and tasks of each stage are clearly described. The correctness and compliance of the design have been verified through waveform simulation and official testing. The design was ultimately validated on FPGA and performance analysis was conducted, indicating that the design can achieve ideal results in practical applications.