Probability-based mapping approach for an application-aware networks-on-chip architectures
Deepa Perumal, Aravindhan Alagarsamy, Sundarakannan Mahilmaran, G.C. Cardarilli, Seok‐Bum Ko · Nano Communication Networks · 2024
In a digital and automation era, on-chip multi-core architecture plays a vital role in effective communication in the field of very large-scale integrated circuits (VLSI). In this paper, we propose a unique mapping approach in which a probability-based core selection from the application benchmark into the center to eccentric way of placement of cores in the standard network architecture improves the performance of networks-on-chip (NoC). The proposed approach utilizes a structured mapping strategy, in contrast to the random mapping. This characteristic renders the proposed method a robust solution for a diverse range of NoC architectures irrespective of scale. The proposed approach provides better quality of service (QoS) with optimal total communication bandwidth and average hop count . The performance of the proposed mapping approach is validated with various experiments over standard and real-time benchmarks. The investigation results indicate that the total communication cost over real-time NoC benchmarks for the proposed mapping approach offers 43.06%, 22.75%, and 16.69% average improvement over CastNet, NMAP, and mapGtoM respectively. Furthermore, we adopt uniform geometric and shuffled traffic patterns to identify the latency and throughput of the proposed probability-based mapping approach. The investigation results indicate that the proposed mapping approach outperforms existing mapping procedures.