MEIN: A Multicast-Efficient Interconnect Network for Multi-Chiplet DNN Accelerators
Hao Chen, Xuyan Wang, Jinming Zhang, Han Xiao, Siqi Cai, Yaoyao Ye, Guanghui He · 2024
Multi-chiplet DNN accelerator is a promising solution to balancing performance and cost. However, the limited communication bandwidth between chiplets exacerbates the performance bottleneck of the interconnect network. Besides, in DNN dataflows, the same weight or activation is often shared by multiple processing elements (PEs). One-to-many dataflows, also known as multicast, are widespread. Existing works lack specific optimizations for DNN dataflows, thereby yielding suboptimal multicast efficiency. To overcome these challenges, we propose MEIN, a Multicast-Efficient Interconnect Network for multi-chiplet DNN accelerators. Firstly, we introduce a highly efficient routing algorithm tailored for DNN dataflows. It optimizes the multicast tree structure to reduce path latency, while also improving the path selection mechanism to minimize link contention. Secondly, we propose a lightweight router microarchitecture that enhances the hardware resource utilization by simplifying multicast ports. Based on the gem5 simulator, our evaluation demonstrates that MEIN achieves the latency reduction by 19.6%-81.9% as compared to the state-of-the-art related works.