A High-throughput Impedance Measurement IC with Baseline-Canceling Peak Detector
Asra Malik, Soon-Jae Kweon, Karam Ellahi, Muhammad Abrar Akram, Song-I Cheon, Yoontae Jung, Minkyu Je, Hammad M. Cheema, Sohmyung Ha · 2024
This paper presents a novel high-throughput impedance measurement integrated circuit (IC) with baseline cancellation for neural EIT applications. The proposed technique uses a peak detector to obtain impedance magnitude every cycle. After taking the peak, the peak detector is reset to a DC baseline voltage. And, the signal swinging between the amplitude and the reset baseline is further amplified, allowing to measure small impedance variations even with a large baseline. The proposed IC fabricated in a 180-nm standard CMOS process can measure impedance variations of >0.1% baseline can be measured, while achieving high throughput of 100 kS/s at 100 kHz input frequency. Scalable design allows the proposed IC to support a wide frequency range from 100 Hz to 100 kHz with a power consumption from 31 μW to 39 μW from a 1.2-V supply.