A Novel Low-Dropout Regulator Architecture for Fast Transient Response with Impedance Adaptation in 90-nm CMOS Process
Abu Nayem Md. Noman, Mahmud Hassan Sohan, Ali Ahmed Afridi · 2023
In this research, a novel low-dropout regulator (LDO) architecture for the 90 nm CMOS technology is introduced. An impedance-adapting compensation approach is proposed, and a faster transient response is also introduced as compared to the conventional LDO architecture. The design provides a decent loop gain for both high and low frequencies. An effective frequency and transient response are achieved throughout the whole range by using a load-tracking strategy to reduce the impact of load fluctuations. The architecture was designed in Cadence Virtuoso and Assura simulator and was used to verify the results. The results indicate that the output voltage regulation of the circuit, ranging from 1.4 V to 2.8 V, is capable of accommodating a current capacity of 6 A. Furthermore, it exhibits a maximum dropout voltage of 118 mV. The data reveals that during load transitions between 300 mA and 5.5 A, there were overshoot voltages of 29.3 mV and undershoot voltages of -22.6 mV. Additionally, the system demonstrates power supply rejection of -53 dB at 10 kHz and -23 dB at 1 MHz. It also exhibits a load regulation of 0.5 mV/A and a line regulation of 0.08 mV/V, among other features.