Comparative Study on 4-Bit Adders and Multipliers with Hardware Implementation
Sabitabratta Bhattacharya, Sam Narasimhan, Rohanth Hari M · 2024
This comparative study investigates the performance of 4-bit adders and multipliers, utilizing various architectural designs. The analysis encompasses circuit complexity, delay, power consumption, and area utilization. Moreover, the study underscores the trade-offs inherent in selecting adder and multiplier architectures, offering invaluable insights for optimizing digital circuits. Notably, the implementation is conducted using Intel's DE10 Lite hardware tool, enriching the findings with real-world hardware experimentation. The results contribute additional depth to adder and multiplier selection processes, providing a robust foundation for developing efficient and high-performance computing systems.