Detection of Voltage Droop-Induced Timing Fault Attacks Due to Hardware Trojans
Jonti Talukdar, Akshay Vyas, Krishnendu Chakrabarty · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2024
Recent breakthroughs in heterogeneous integration (HI) using 2.5-D/3-D packaging technology have led to several advances in the semiconductor industry, increasing yield while reducing overall cost and time-to-market. However, the diversification of the HI supply chain has led to several sources of distrust due to the use of black-boxed third-party intellectual property (IP), outsourced fabrication, assembly and test facilities during the design and manufacturing process. We demonstrate the susceptibility of chiplet IPs to timing failure due to voltage droop in the power distribution network (PDN) induced by the insertion of chiplet level ring-oscillator (RO)-based hardware Trojans. We present an end-to-end methodology for design, placement, and insertion of RO-based Trojans in chiplet designs followed by characterizing their contribution to the dynamic voltage droop induced within the on-chip PDN. We quantify this PDN impact on timing paths and develop a systematic method to rank the susceptibility of different data paths toward a voltage droop event. We utilize this presilicon security analysis framework to evaluate voltage droop-based attack susceptibility for a variety of IPs, including some from the CEP benchmark. We also develop a machine learning-guided time-series anomaly detection framework to detect voltage droop-based anomalies on functional workloads running on different benchmarks, demonstrating the effectiveness of an convolutional autoencoders in detecting voltage droop-induced timing anomalies.