MRPHS: A Verilog RTL to C++ Model Compiler Using Intermediate Representations for Object-oriented Model-driven Prototyping
Tobias Strauch · 2023
The compilation of Verilog RTL designs into C or C++ models to be used in model-driven prototyping environments has recently become the subject of new research projects and publications. Our work describes the process of compiling Verilog RTL designs into C++ models which support intermediate representations. Depending on the given library, the compiled code can then be used for user-defined simulation targets, especially for object-oriented, model-driven prototyping scenarios. This allows user defined data, e.g. coverage points, to be propagated and modified throughout the design during simulation. We present examples such as symbolic RTL simulation, power consumption estimation on RTL as well as RTL ATPG for in-system stuck-at testing. We also present run-time comparison results.