Booth Multiplier Design and Implementation Using NEXYS-4 ARTIX-7 FPGA Board
Suman Lata Tripathi, Abhishek Kumar, Sandhya Avasthi, Mufti Mahmud · 2024
Multiplier is an important block in many DSP processor that uses considerable IC area. A prefabrication design of such block at RTL level is useful for performance optimisation in number of components, power consumption and delay. In this work, a booth multiplier was designed through Vivado 2019.1 and implemented using NEXYS-4 ARTIX-7 FPGA Board with onboard seven segment display. Booth multiplication algorithm is a 2’s complement multiplication algorithm that multiplies two signed binary digits efficiently. Different from the conventional multiplication process, in booth multiplication, the multiplicand may be added to the partial product, subtracted from the partial product or left unchanged depending on the conditional statements provided. The booth multiplier was implemented in the FPGA board and has produced the expected results for every input. Through design and synthesis process, an RTL level model is obtained describing the onboard device utilisation and total power consumption including static and dynamic powers. In the FPGA board, the inputs are represented by switches, and the output is displayed through the seven segments. In this design, the booth multiplier accepts inputs from 0 to 15 only, both positive and negative.