VIPER: A VTR Interface for Placement with Error Resilience
Kate Thurmer, Vaughn Betz · 2024
The open source Verilog-to-Routing (VTR) tool flow can produce legal placement solutions for arbitrarily complex FPGA architectures and is thus widely used for novel device development as well as CAD tool research. VTR’s versatility is enabled by both its robust device modeling capability and its use of pre-placement clustering to abstract away complexity and maintain scalability. Clustering is not always necessary; recent academic tools demonstrate that delaying or omitting it can improve result quality for some device architectures. By incorporating a variety of external placement tools, VTR can maintain both versatility and result quality as FPGAs scale and diversify. Tool developers can benefit as well from access to VTR; however, due to VTR’s complex, hierarchical device modeling, its place and route interface requires a level of detail and accuracy that is beyond the scope of many external tools. To lower the barrier to interoperability, we introduce a VTR Interface for Placement with Error Resilience (VIPER). VIPER constructs a complete, legal, VTR-compatible clustering and placement solution based on a simplified and potentially illegal input placement.