Systolic Array-Based Many-Core Processor with Simultaneous Dual-Instruction Issuance
Yuxi Tan, Masaru Nishimura, Riadh Ben Abdelhamid, Bingjie Guo, Qixiang Gao, Yoshiki Yamaguchi · 2024
In the past quarter-century, many-core processors have emerged as a response to the slowdown of Moore’s Law, aiming to boost computational performance and energy efficiency. However, these processors face challenges in efficiently sharing data among processing elements due to memory access constraints, which are not easily addressed by conventional Single-Instruction Multiple-Data (SIMD) and Multiple-Instruction, Multiple-Data (MIMD) architectures. New approaches, such as thread-based execution models like Single-Instruction Multiple-Thread (SIMT), have been proposed to manage massively distributed processing elements. Nevertheless, opportunities for enhancing data sharing persist. This article introduces a novel Dual-Instruction Multiple-Data (DIMD) architecture, bridging the gap between SIMD and MIMD architectures to tackle these challenges. We implement this architecture by extending the RISC-V instruction set. Experimental results demonstrate that our approach can achieve up to double the energy efficiency of traditional SIMD architectures.