CAD Techniques for NoC-Connected Multi-CGRA Systems
Hongsong Wei, Omkar Bhilare, Hamas Waqar, Jason Helge Anderson · 2024
Coarse-grained reconfigurable arrays (CGRAs) are programmable hardware platforms that are a means of realizing application accelerators. A CGRA is a 2D array of configurable processing elements (PEs), that connect to one another through programmable interconnects. PEs and interconnects in CGRAs are configurable at the word level, as opposed to at the bit level in FPGAs. A network-on-chip (NoC) is an on-chip communications system comprising routers and links, where data is packet-switched. NoCs provide more scalable communication vs. traditional on-chip busses or crossbars. In this paper, we propose an NoC-connected multi-CGRA system, where multiple modest-sized CGRAs communicate using an NoC. We introduce CAD techniques that partition and place an application across the “distributed” NoC-connected CGRAs. We study the quality and runtime of the CAD techniques on a system having sixteen 4 × 4 CGRAs connected together using a 2D mesh NoC.