Securing Against Side-Channel Attacks With Wide-Range In Situ Random Voltage Dithering on Async-Logic AES Engine
Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Kwen‐Siong Chong, Bah‐Hwee Gwee · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2024
We present a wide-range in situ random voltage dithering (WIS-RVD) on async-logic advanced encryption standard (AES) engine to counteract side-channel attacks (SCAs). There are three contributions in this brief. First, we propose the WIS-RVD based on a dual-rail asynchronous-logic (async-logic) AES engine, leveraging on the self-timed clockless operations for robust encryption under dynamic voltage and timing variations. Second, we propose an in situ voltage dithering to dither the supply voltage instantaneously during the encryption, without the requirement of additional control circuits for clock modulation, to increase the SCA resistance. Third, we propose a wide-range voltage swing technique that spans from 0.3 V (subthreshold) to 1.1 V (above threshold), obfuscating the transistor’s current models between subthreshold and threshold voltage to further enhance SCA resistance. We perform comprehensive SCA evaluations with 50-M power and EM measurements, and the SCA evaluations show that our proposed WIS-RVD on async-logic AES accelerator can resist SCAs with 50-M measurements, i.e.,$\gt 2083\times $and$\gt 2778\times $improvement for power and EM SCAs, respectively, when compared to the standard synchronous-logic AES.