A Construct for Software-Like Hardware RTL Code in HDLRuby
Lovic Gauthier, Yohei Ishikawa · 2024
We propose a novel register transfer level (RTL) construct, called sequencer, in the hardware description language HDLRuby aimed at facilitating the description of sequential circuits. Compared to the standard RTL processes, this construct supports all the software-oriented statements including loops and recursive functions in addition to the hardware RTL elements. We compared qualitatively and quantitatively the usage of this construct in HDLRuby, with the Vitis HLS high-level synthesis tool by implementing several software C applications on FPGA. While using HDLRuby required rewriting the code to match its syntax, the design effort for both approaches proved to be similar. Moreover, higher performance, more flexibility, and a wider range of supported applications were achieved for HDLRuby with sequencers.