Execution of Reconfiguration System on Chip Design for Internet of Things
Ipseeta Nanda, J. Midhunchakkaravarthy · 2023
To address the demand for additional resources on the DPR stands for dynamic partial reconfiguration and field programmable gate array. was introduced. PDR can alter the system’s efficiency and functioning to make room for additional hardware modules, reduce power consumption, and conserve fabric area. PDR entails designing modules that are self-contained and able to be sequentially loaded in the same fabric region. The authors of this work modify a small portion of the FPGA at runtime to add new functionality, leaving the other portions of the device unchanged. A tool developed by XILINX called PLANAHEAD, which can construct systems that are changeable for every VIRTEX field programmable gate array during runtime, can help simplify the complications of this process. The first graphical environment for partial reconfiguration, PLANAHEAD offers the freedom to adapt a design in the field, save power consumption, and save board area.