Randomization Approaches for Secure SAR ADC Design Resilient Against Power Side-Channel Attacks
Sumanth N. Karanth, Sirish Oruganti, Meizhi Wang, Jaydeep P. Kulkarni · 2024
This work aims to enhance the hardware security of mixed-signal circuits, particularly Successive Approximation Register Analog-to-Digital Converters (SAR-ADCs), through the introduction of an innovative circuit technique aimed at bolstering their resistance against power side-channel attacks (PSCAs). A comprehensive mathematical analysis of PSCAs targeting SARADCs is undertaken, with specific emphasis placed on attacks made by tapping the reference voltage node (VREF). These insights lead to the introduction of a novel circuit technique, Enhanced Randomized Reference SAR (ERR-SAR), intended to mitigate PSCAs affecting these vulnerable nodes. To assess the efficacy of the proposed solution, a SAR-ADC is designed using a 65nm CMOS technology, facilitating a comparative evaluation of performance and security robustness with and without the ERR-SAR protection scheme. The results demonstrate a substantial 505% improvement in security against PSCAs achieved through ERR-SAR, accompanied by minimal tradeoffs with power, performance, and area. The practical efficacy of ERRSAR in fortifying SAR-ADC security with minimal overhead is emphasized, providing significant advantages in safeguarding these circuits against side-channel attacks.