An improved current comparator with digital feedback
Cheng Zhou, Fanchao Zhou, Jinhui Liang, Jiangping He · 2024
Based on the DB HiTek 0.18 CMOS process, this paper presents an improved dynamic current comparator. This circuit operates effectively under a power supply voltage of 1.2V with an error margin of ±10%. By employing digital logic feedback technology, the comparator's output is latched after the comparison, and a logic circuit controls the comparator's shutdown. The circuit only consumes dynamic power, reducing the average power consumption. Using Cadence software for simulation, the results indicate that the improved current comparator achieves a comparison accuracy of 50nA, dynamic power consumption of 126uw, average power consumption ranging from 10% to 80% of dynamic power, a delay of 10.55 ns, and is minimally affected by process variations. It is suitable for low-voltage, low-power current-mode integrated circuits.